1. Field of the Invention
This invention relates to a semiconductor device and is particularly suitable for a semiconductor device incorporating both an analog circuit and a digital circuit.
2. Description of the Related Art
FIG. 1 shows a conventional vertical npn bipolar transistor used as a high-speed bipolar transistor. As shown in FIG. 1, in the high-speed bipolar transistor 101 in form of the vertical npn bipolar transistor, an n-type epitaxial layer 103 is grown on a p-type silicon (Si) substrate 102. The Si substrate 102 has formed an n.sup.+ -type buried diffusion layer 104 in its upper portion so as to bite into a lower portion of the n-type epitaxial layer 103. Formed on the n-type epitaxial layer 103 is a device separating region 105 made of an oxide to isolate the high-speed bipolar transistor 101 from another device. Formed under the device separating region 105 is a p.sup.+ -type device separating diffusion region 106 extending into the Si substrate 102.
A p-type base layer 107 is formed in an upper portion of the n-type epitaxial layer 103 surrounded by the device separating region 105, and a p.sup.+ -type graft base layer 108 is formed in opposite ends of the base layer 107 in connection therewith. An n.sup.+ -type emitter layer 109 lies on the base layer 107, and an n.sup.+ -type collector lead-out layer 110 is formed in the n-type epitaxial layer 103 in connection with the buried diffusion layer 104 in a location distant from the graft base layer 108.
A first oxide film 111 lies on the n-type epitaxial layer 103 and has formed an aperture 112 above the graft base layer 108. Formed on the first oxide film 111 is a base lead-out electrode 113 connected to the graft base layer 108 through the aperture 112. The base lead-out electrode 113 is covered by a second oxide film 114 formed on the first oxide film 111. The second oxide film 114 has formed an aperture 114a above the emitter layer 109, and its inner wall is covered by a side wall film 116 made of silicon oxide (SiO.sub.2). The inner side of the side wall film 116 is used as an emitter aperture 116a through which an emitter lead-out electrode 117 is connected to the emitter layer 109.
Further formed are a base electrode 118 connected to the base lead-out electrode 113 through an aperture 114b formed in the second oxide film 114, an emitter electrode 119 connected to the emitter lead-out electrode 117 through the emitter aperture 116a, and a collector electrode 120 connected to the collector lead-out layer 110 through an aperture 114c formed in the second oxide film 114 and an aperture 111a formed in the first oxide film 111.
Next shown is a conventional vertical npn bipolar transistor used as a high voltage-resistant bipolar transistor. As shown in FIG. 2, in the high voltage-resistant bipolar transistor 121 in form of the vertical npn bipolar transistor, grown on a p-type Si substrate 122 is an n-type epitaxial layer 123 thicker than the n-type epitaxial layer 103 of the high-sped bipolar transistor 101 shown in FIG. 1. The Si substrate 122 has formed an n.sup.+ -type buried diffusion layer 124 in its upper portion to bite into a lower portion of the n-type epitaxial layer 123. The buried diffusion layer 124 is deeper than the buried diffusion layer 104 in the high-speed bipolar transistor 101. Formed in the n-type epitaxial layer 123 is a device separating region 125 to isolate the high voltage-resistant bipolar transistor 122 from another device. Formed below the device separating region 125 is a p.sup.+ -type device separating diffusion region 126 extending into the Si substrate 122.
A p-type base layer 127 is formed in an upper portion of the n-type epitaxial layer 123 surrounded by the device separating diffusion region 126, and a p.sup.+ -type graft base layer 128 is formed in opposite sides of the base layer 127 in connection therewith. An n.sup.+ -type emitter layer 129 lies on the base layer 127, and an n.sup.+ -type collector lead-out layer 130 is formed in the n-type epitaxial layer 123 in connection with the buried diffusion layer 124.
A first oxide film 131 lies on the n-type epitaxial layer 123 and has formed an aperture 131a above the graft base layer 128. Formed on the first oxide film 131 is a base lead-out electrode 132 connected to the graft base layer 128 through the aperture 131a. The base lead-out electrode 132 is covered by a second oxide film 133 formed on the first oxide film 131. The second oxide film 133 has formed an aperture 133a above the emitter layer 129, and its inner wall is covered by a side wall film 134 made of SiO.sub.2. The inner side of the side wall film 134 is used as an emitter aperture 134a through which an emitter lead-out electrode 135 is connected to the emitter layer 129.
Further formed are a base electrode 136 connected to the base lead-out electrode 132 through an aperture 133b formed in the second oxide film 133, an emitter electrode 137 connected to the emitter lead-out electrode 135 through the emitter aperture 134a, and a collector electrode 138 connected to the collector lead-out layer 130 through an aperture 133c formed in the second oxide film 133 and an aperture 131b formed in the first oxide film 131.
Next explained are distributions of impurity concentration in the depth direction of the high-speed bipolar transistor 101 and the high voltage-resistant bipolar transistor, both taken along the A--A lines, with reference to FIGS. 3 and 4. In these drawings, the ordinate shows impurity concentration in logarithm of arbitrary unit, and the abscissa shows the depth from the surface of the epitaxial layers 103, 123 formed on the Si substrate 102, 122.
As shown in FIG. 3, the distribution of impurity concentration in the depth direction of the high-speed bipolar transistor 121 is characterized in that the n-type epitaxial layer 103 is thin and exhibits a high impurity concentration.
In the impurity concentration of the high voltage-resistant bipolar transistor 121 in FIG. 4, the n.sup.+ -type emitter layer 129 and the p-type Si substrate 122 have substantially the same impurity concentrations as those of the emitter layer 109 and the Si substrate 102 of the high-speed bipolar transistor 101, but the n-type epitaxial layer 123 has a larger thickness and a lower impurity concentration than those of the n-type epitaxial layer 103 of the high-speed bipolar transistor 101. Additionally, the p-type base layer 127 is generally thicker than the base-layer 107 of the high-speed bipolar transistor 101.
To realize a high voltage-resistance BVcbo in a bipolar transistor, in general, its n-type epitaxial layer must have a low impurity concentration and an ample thickness.
Next shown in FIG. 5 is a conventional bipolar CMOS IC having an n-channel MOS transistor and a vertical npn bipolar transistor. As shown in FIG. 5, in the n-channel MOS transistor 141, an n-type epitaxial layer 143 is grown on a p-type Si substrate 142, and a p.sup.+ -type diffusion layer 144 is formed in an upper portion of the Si substrate 142 and in the n-type epitaxial layer 143. The n-type epitaxial layer 143 has formed a device separating region 145 made of an oxide to isolate the n-channel MOS transistor 141 from another device. A p-type well region 146 is formed in a portion surrounded by the device separating region 145 which has formed, in its upper portion, an n.sup.+ -type source region 147 and a drain region 148 in self alignment, and a p.sup.+ -type diffusion region 149. A gate electrode 151 covered by an oxide film 152 is formed on a portion of the p-type well region 146 between the source region 147 and the drain region 148 via a gate oxide film 150. The oxide film 152 covers the entire surface of the n-type epitaxial layer 143. The oxide film 152 has formed apertures in predetermined portions. Through the apertures, the source electrode 153 is formed and connected to the source region 147 and the diffusion region 149, and the drain electrode 154 is formed and connected to the drain region 148.
Next explained is the vertical npn bipolar transistor 155 formed in the n-type epitaxial layer 143 on the Si substrate 142. Construction of the vertical npn bipolar transistor 155 is similar to the high-speed bipolar transistor 101 and the high voltage-resistant bipolar transistor 121 referred to above. That is, formed in an upper portion of the Si substrate 142 is an n.sup.+ -type buried layer 156 diffused into the n-type epitaxial layer 143, and an n.sup.+ -type collector lead-out layer 157 is formed in connection with the buried layer 156. A p.sup.+ -type device separating diffusion region 158 is formed below the device separating region 145 of the n-type epitaxial layer 143. A p-type base layer 159 is formed in an upper portion surrounded by the device separating region 145, and a p-type graft base layer 160 is formed on opposite sides of the base layer 159 in connection therewith. Formed on the base layer 159 is an n.sup.+ -type emitter region 161. Formed on the n-type epitaxial layer 143 is a first oxide film 162 which is made simultaneously with the gate oxide film 150 in the n-channel MOS transistor 141, and a base lead-out electrode 163 connected to the graft base layer 160 is formed on the first oxide film 162. The base lead-out electrode 163 is covered by the oxide film 152, and a side wall film 164 made of SiO.sub.2 is formed in an aperture made in the oxide film 152 above the base layer 160. The inner side of the side wall film 164 is used as an emitter aperture 164a, and an emitter lead-out electrode 165 in form of a polycrystalline Si film is formed and connected to the emitter layer 161 through the emitter aperture 164a.
Further formed are a base electrode 166 connected to the base lead-out electrode 163 through another aperture of the oxide film 152, an emitter electrode 167 connected to the emitter lead-out electrode 165 through another aperture of the oxide film 152, and a collector electrode 168 connected to the collector lead-out layer 157 through another aperture of the oxide film 152 and an aperture formed in the first oxide film 162.
In the bipolar CMOS IC explained above, part of a current i passing through the n-channel MOS transistor flows into the p-type Si substrate 142 through the p-type well region 146, and causes the Si substrate 142 to change in potential. It invites changes in value of the junction capacitance composed of the n.sup.+ -type buried layer 156 of the bipolar transistor 155 and the Si substrate 142, and hence causes various parameters to vary. Especially in an analog/digital mixed bipolar CMOS IC, this phenomenon causes the problem of so-called analog/digital interference noise, in which digital noise enters in an analog signal, and it is a serious problem in a bipolar CMOS IC.
For the purpose of reducing the analog/digital interference noise, it has been proposed to use a npn junction to separate the p-type well region 146 and the Si substrate 142 in the n-channel MOS transistor as shown in FIG. 6. FIG. 7 is a graph showing impurity concentration distribution along the A--A line of FIG. 6.
As shown in FIG. 6, the Si substrate 142 has formed an n-type separation layer 169, and p-type well regions 146 and 170 a of a retrograde structure overlie the n-type separation layer 169. As shown in FIGS. 6 and 7, even when part of the current passing through the n-channel MOS transistor 141 flows into the p-type well regions 146, 170, the n-type separation region 169 prevents it from reaching the Si substrate 142, and therefore reduce the analog/digital interference noise in the bipolar CMOS IC.
However, when the high-speed bipolar transistor 101, high voltage-resistant bipolar transistor 121 and MOS transistor are formed on a common semiconductor substrate, the following problem arises. That is, the n-type epitaxial layer 103 in the high-speed bipolar transistor 101 must have a high impurity concentration and a small thickness to suppress the Kirk effect of the collector whereas the n-type epitaxial layer 123 must has a low impurity concentration and a large thickness to ensure a high resistivity to voltage.
Moreover, if the n-type separation layer is used in the part of the MOS transistor in a bipolar CMOS semiconductor device including the bipolar transistors and the MOS transistor, then a step therefore must be added to the manufacturing process of the bipolar CMOS semiconductor device, and it further increases the manufacturing cost of the bipolar CMOS semiconductor device which is originally expensive, in general.